Conventionally, DRAMs and SDRAMs are known as memories that require refresh operations, are mounted, for example, on a memory board shown in FIG. 7, and are incorporated in and used in various information processing devices.
The conventional memory board 100 shown in FIG. 7 comprises a memory 102, a memory controlling unit 104, an external interface unit 106, an ECC circuit 108, a refresh request generating unit 110, and a patrol controlling unit 112.
The memory 102 is comprised of a DRAM, SDRAM, or the like; therefore, a refresh operation for retaining memory contents has to be periodically executed.
The memory controlling unit 104 outputs control signals at the timing, which is determined by a used device, and controls write and read of data with respect to the memory 102. The external interface unit 106 interfaces with a processor or a higher-level control device.
The ECC circuit 108 generates an error detecting and correcting code (check bit) according to control from the memory controlling unit 104 upon data write to the memory 102, adds the code to data, and writes the data to the memory 102; and, when the data is read from the memory 102, the ECC circuit checks normality of the data by using the error detecting and correcting code of the read data and, if a correctable error is detected, corrects the error of the data. As an algorithm for generating the error detecting and correcting code in the ECC circuit 108, for example, a single-error-correcting and double-error-detecting code is used.
The refresh request generating unit 110 is activated at a refresh interval, which is defined by specifications of the memory 102, gives a trigger to the memory controlling unit 104 so as to issue a refresh command, and causes the memory controlling unit 104 to issue the refresh command to the memory 102 so as to cause the memory 102 to carry out a refresh operation.
The patrol controlling unit 112 reads data from the memory 102 at a constant cycle, checks normality of the data by using the ECC circuit 108, and, if a correctable error is detected, corrects and writes back the data to the memory 102.
Operation of such memory board 100 is as follows. Based on an input/output request (write command or read command) received through the external interface unit 106, the memory controlling unit 104 outputs a control signal of the memory 102 and carries out write or read of data.
Upon write of data, the ECC circuit 108 is controlled at the same time; an error correcting code is generated from the data, added to the data, and written to the memory 102. Upon read of data, the memory controlling unit 104 controls the ECC circuit 108, carries out error detection according to the read data and the error correcting code thereof, corrects an error bit, and outputs the data.
When a single-error-correcting and double-error-detecting code is used as an error check code, single errors can be corrected; however, double errors cannot be corrected. Regarding detection of a double error, which cannot be corrected, error detection is notified to a processor, and the processor, which has received the notification, issues a correction write request.
The external interface unit 106 carries out communication with an external processor or a higher-level control device and requests the memory controlling unit 104 to write or read data to or from the memory 102. When, for example, a double error, which cannot be corrected, is detected by the ECC circuit 108, the external interface unit 106 relays a notification of the error detection to the processor or the higher-level control device.
The processor or the higher-level control device requests correction write with respect to this error notification, thereby recovering the error of the memory 102.
The refresh request generating unit 110 gives a refresh request to the memory controlling unit 104 at a cycle which is set in advance. When the memory controlling unit 104 receives the refresh request from the refresh request generating unit 110, the memory controlling unit 104 issues a refresh command to the memory 102. The memory 102, which has received the refresh command, subjects a memory array, which is specified by row addresses and column addresses, to one refresh operation by sequentially specifying the row addresses.
The patrol controlling unit 112 periodically reads the memory 102 and checks normality of data by the ECC circuit 108. When a single error is detected by the ECC circuit 108, corrected data is written back to the memory. This patrol of checking normality of the data is carried out for the entire address region of the memory 102.    Patent Document 1: Japanese Patent Application Laid-Open (kokai) No. 2002-25299    Patent Document 2: Japanese Patent Application Laid-Open (kokai) No. S56-165989    Patent Document 3: Japanese Patent Application Laid-Open (kokai) No. S55-163685    Patent Document 4: Japanese Patent Application Laid-Open (kokai) No. S56-019599